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ordering number : enn * 6477 51200rm (ot) no. 6477-1/12 overview the LC4132C is a segment driver for large-scale dot matrix lcds. the LC4132C latches 240 bits of display data sent from the controller (in 4- or 8-bit parallel units) and generates the lcd drive signals. the LC4132C and the lc4102c common driver form a chip set that can drive a large-screen lcd panel. features cmos (p-substrate) high voltage process lcd drive voltage: 36 v logic system supply voltage: 2.7 to 5.5 v fcp max: 12 mhz (v dd = 5 v ?0%), 10 mhz (v dd = 2.7 to 4.5 v) slim chip can be switched between 4-bit an 8-bit parallel input. output direction switching display off function that holds the lcd drive voltages at fixed levels. display duty: 1/160 to 1/480 supports cog (chip on glass) mounting. (gold bump pads are used.) LC4132C sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan dot matrix stn lcd segment driver cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
block diagram no. 6477- 2 /12 LC4132C o1 v0 v0 4 level lcd drive circuit (240 bits) output control level shifter 2nd latch (240 bits) bits control address decoder address counter chip disable & latch control 1st latch (8 bits 30) v2 v3 v5 vddh vdd vss eio2 v2 v3 v5 vddh disp m load bs d0 to d7 cp r/l eio1 o2 o3 o4 o238 o239 o240
no. 6477- 3 /12 LC4132C the electrical characteristics listed below apply when packaged in the sanyo pga-208 package. notes: 1. d0 to d7, load, cp, r/l, disp, m, eio1, eio2, bs 2. the following relationships must hold for v0, v2, v3, and v5: v ddh 3 v0 3 v2 3 v ddh ?7 v, and 7 v 3 v3 3 v5 3 v ss . notes: 3. d0 to d7, load, cp, r/l, m, disp, bs, eio1, eio2 4. the following relationships must hold for v0, v2, v3, and v5: v ddh 3 v0 3 v2 3 v ddh ?7 v, and 7 v 3 v3 3 v5 3 v ss . at power on: the logic system power supply must be applied before the high-voltage system power supply. (or they must both be a pplied at the same time.) at power off: the high-voltage system power supply must be turned off before the logic system power supply. (or they must both be turned off at the same time.) note: 5. the clock rise time (tr) and the clock fall time (tf) must meet the conditions (1) and (2) shown below. 1 ?tw (cph) ?tw (cpl) fcp (1) tr, tf < (2) tr, tf 50 ns 2 parameter symbol conditions ratings unit min typ max v dd max v dd ?.3 7.0 v maximum supply voltage v ddh max v ddh ?.3 40.0 v v ss max v ss ?.3 0.3 v v in * 1 ?.3 v dd + 0.3 v input voltage v0, v2 v0, v2 * 2 v ddh ?7.0 v ddh + 0.3 v v3 v3 * 2 ?.3 v ss + 7.0 v v5 v5 * 2 ?.3 0.3 v operating temperature topr ?0 +75 c storage temperature tstg ?5 +125 c absolute maximum ratings at v ss = 0 v parameter symbol conditions ratings unit min typ max v dd v dd 2.7 5.5 v supply voltage v ddh v ddh 20 36 v v ss v ss 0 v input high-level voltage v ih * 3 0.8 v dd v dd v input low-level voltage v il * 3 0 0.2 v dd v v0, v2 v0, v2 * 4 v ddh ?7.0 v ddh v input voltage v3 v3 * 4 0 v ssh + 7.0 v v5 v5 * 1 0 v allowable operating ranges at ta = ?0 to +75 c, v ss = 0 v parameter symbol conditions ratings unit min typ max cp clock frequency fcp cp 12 mhz high-level load pulse width tw (ldh) load 50 ns high-level clock pulse width tw (cph) cp 20 ns low-level clock pulse width tw (cpl) cp 20 ns load/cp setup time tsu (ld) load, cp 100 ns load/cp hold time tho (ld) load, cp 200 ns data/cp setup time tsu (cp) cp, d0 to d7 10 ns data/cp hold time tho (cp) cp, d0 to d7 10 ns eio input setup time tsu (ei) cp, eio1, eio2 24 ns clock rise time tr load, cp * 5 50 ns clock fall time tf load, cp * 5 50 ns v dd = 5 v 10%, ta = ?0 to +75 c, v ss = 0 v
no. 6477- 4 /12 LC4132C note: 6. the clock rise time (tr) and the clock fall time (tf) must meet the conditions (1) and (2) shown below. 1 ?tw (cph) ?tw (cpl) fcp (1) tr, tf < (2) tr, tf 50 ns 2 parameter symbol conditions ratings unit min typ max cp clock frequency fcp cp 10 mhz high-level load pulse width tw (ldh) load 50 ns high-level clock pulse width tw (cph) cp 37 ns low-level clock pulse width tw (cpl) cp 37 ns load/cp setup time tsu (ld) load, cp 100 ns load/cp hold time tho (ld) load, cp 350 ns data/cp setup time tsu (cp) cp, d0 to d7 35 ns data/cp hold time tho (cp) cp, d0 to d7 35 ns eio input setup time tsu (ei) cp, eio1, eio2 30 ns clock rise time tr load, cp * 6 50 ns clock fall time tf load, cp * 6 50 ns v dd = 2.7 to 4.5 v, ta = ?0 to +75 c, v ss = 0 v notes: 7. d0 to d7, load, cp, r/l, m, disp, eio1, 2, bs 8. v o is the voltage applied by an on-state output, v0 = v ddh , v2 = 18/20 (v ddh ?v ss ), v3 = 2/20 (v ddh ?v ss ), v5 = v ss . 9. measured when either load = 28 khz, cp = 10 mhz, and m = 75 hz, or with no load and input at v ih = v dd or v il = v ss . 10. the current drain in standby mode. or when eion (input) = v dd . parameter symbol conditions ratings unit min typ max input high-level voltage i ih v in = v dd * 7 5 a input low-level voltage i il 1 v in = v ss * 7 ? a output high-level voltage v oh i o = ?.4 ma: eio1, eio2 v dd ?0.4 v dd v output low-level voltage v ol i o = 0.4 ma: eio1, eio2 v ss 0.4 v v ddh = 36 v * 8 output on resistance r out v0 ?v o = 0.5 v, v2 ?v o = 0.5 v 1 3 k v o ?v3 = 0.5 v, v o ?v5 = 0.5 v : o1 to o240 i dd v dd = 2.7 to 5.5 v 5.0 ma current drain i ddh v dd = 2.7 to 5.5 v, v ddh = 32 v * 9 3.0 ma v dd = 5 v 10%, v ddh = 36 v 3.0 ma i st * 10 500 a electrical characteristics at ta = ?0 to +75 c, v dd = 2.7 to 5.5 v, v ss = 0 v
no. 6477- 5 /12 LC4132C parameter symbol conditions ratings unit min typ max eio output delay time td (eo) 30 pf capacitance load: cp, eio1, eio2 40 ns load/eio output delay time td (leo) 30 pf capacitance load: load, eio1, eio2 70 ns load/on delay time td (ldo) 100 pf capacitance load: load, o1 to o240 700 ns m/on delay time td (mo) 100 pf capacitance load: m, o1 to o240 700 ns switching characteristics at ta = ?0 to +75 c, v ss = 0 v parameter symbol conditions ratings unit min typ max eio output delay time td (eo) 30 pf capacitance load: cp, eio1, eio2 80 ns load/eio output delay time td (leo) 30 pf capacitance load: load, eio1, eio2 130 ns load/on delay time td (ldo) 100 pf capacitance load: load, o1 to o240 3 s m/on delay time td (mo) 100 pf capacitance load: m, o1 to o240 3 s v dd = 2.5 to 4.5 v timing chart (v ih = 0.8 v dd , v il = 0.2 v dd ) 0.2vdd 0.8vdd tr(ld) tw(ldh) tf(ld) tho(ld) tsu(ld) td(mo) tsu(cp) tho(cp) td(leo) tr(cp) tw(cph) tf(cp) tw(cpl) td(eo) tsu(ei) td(ldo) eion (output) (input to the next stage) v dd = 5 v 10% load cp d0 to d7 m on
no. 6477- 6 /12 LC4132C pin functions pin i/o function lcd drive outputs o1 to o240 o v0 level drive voltage application (selected level) v2 level drive voltage application (unselected level) v3 level drive voltage application (unselected level) v5 level drive voltage application (selected level) v0 v2 v3 v5 i i i i m data disp on h h h v0 h l h v2 l l h v3 l h h v5 * * l v5 r/l eio1 eio2 l in out h out in r/l bs o1 to o240 outputs o1 o2 o3 o4 ? ... o237 o238 o239 o240 l - - - - - - - - h d7 d6 d5 d4 d3 d2 d1 d0 o1 o2 o3 o4 ? ... o237 o238 o239 o240 h - - - - - - - - d0 d1 d2 d3 d4 d5 d6 d7 o1 o2 o3 o4 ? ... o237 o238 o239 o240 l - - - - - - - - l d3 d2 d1 d0 d3 d2 d1 d0 o1 o2 o3 o4 ? ... o237 o238 o239 o240 h - - - - - - - - d0 d1 d2 d3 d0 d1 d2 d3 high-voltage system power supply v ddh logic system power supply v dd gnd v ss lcd off function. when this pin is low, all outputs are held at the v5 level. disp i alternation signal input m i enable i/o enable input: the enable input at the initial stage is fixed at the v ss level, and the enable inputs of later stages are connected to the enable output from the previous stage. enable output: when cascade connection is used, the enable output is connected to the enable input of the next stage. eio1 eio2 i/o i/o data acquisition clock (falling edge) cp i data load clock (falling edge) load i data shift direction setting r/l i parallel data inputs d0 to d7 i input bus width setting. a high level selects 8-bit input, and a low level selects 4-bit input. in 4-bit input mode, d0 to d3 a re used for data acquisition and d4 to d7 must be tied to ground. bs i * don't care
pad assignment no. 6477- 7 /12 LC4132C nc o5 o6 o7 o8 o233 nc v5 nc v5 v5 v3 v3 v3 v2 v2 v2 v0 v0 v0 vddh vddh vddh vss vss vss vdd vdd vdd vdd vdd vdd vdd vss vss vss vss vss vss vss bs bs r/l r/l nc nc disp disp m m load cp cp eio1 load eio1 eio2 eio2 vss vss vss vdd vdd vdd d7 d7 d6 d6 d5 d5 d4 d4 d3 d3 d2 d2 d1 d1 d0 d0 vdd vdd vdd vss vss vss vss vss vss vss vddh vddh vddh v0 v0 v0 v2 v2 v2 v3 v3 v3 v5 v5 v5 nc nc nc nc nc nc nc o1 o2 o3 o4 o234 o235 o236 nc nc nc nc nc nc nc nc o240 o239 o238 o237 origin (0, 0) chip size: 15.7 2.0 mm y (+) x (+)
no. 6477- 8 /12 LC4132C LC4132C pad coordinates pin x coordinate y coordinate bump type pin x coordinate y coordinate bump type nc ?687.0 ?94.0 d v ss ?72.0 ?06.0 a v5 ?587.0 ?94.0 a v ss 7.0 ?06.0 a v5 ?487.0 ?94.0 a v ss 186.0 ?06.0 a v5 ?387.0 ?94.0 a v dd 365.0 ?06.0 a v3 ?287.0 ?94.0 a v dd 544.0 ?06.0 a v3 ?187.0 ?94.0 a v dd 723.0 ?06.0 a v3 ?087.0 ?94.0 a d7 949.0 ?06.0 a v2 ?987.0 ?94.0 a d7 1174.0 ?06.0 a v2 ?887.0 ?94.0 a d6 1399.0 ?06.0 a v2 ?787.0 ?94.0 a d6 1624.0 ?06.0 a v0 ?687.0 ?94.0 a d5 1849.0 ?06.0 a v0 ?587.0 ?94.0 a d5 2074.0 ?06.0 a v0 ?487.0 ?94.0 a d4 2299.0 ?06.0 a v ddh ?387.0 ?94.0 a d4 2524.0 ?06.0 a v ddh ?287.0 ?94.0 a d3 2749.0 ?06.0 a v ddh ?187.0 ?94.0 a d3 2974.0 ?06.0 a v ss ?087.0 ?94.0 a d2 3199.0 ?06.0 a v ss ?987.0 ?94.0 a d2 3424.0 ?06.0 a v ss ?887.0 ?94.0 a d1 3649.0 ?06.0 a v dd ?787.0 ?94.0 a d1 3874.0 ?06.0 a v dd ?687.0 ?94.0 a d0 4099.0 ?06.0 a v dd ?587.0 ?94.0 a d0 4324.0 ?06.0 a v dd ?487.0 ?94.0 a v dd 4446.2 ?94.0 a v dd ?387.0 ?94.0 a v dd 4646.2 ?49.0 a v dd ?287.0 ?94.0 a v dd 4846.2 ?94.0 a v dd ?187.0 ?94.0 a v ss 5046.2 ?94.0 a v ss ?087.0 ?94.0 a v ss 5246.2 ?94.0 a v ss ?987.0 ?94.0 a v ss 5446.2 ?94.0 a v ss ?887.0 ?94.0 a v ss 5646.2 ?94.0 a v ss ?787.0 ?94.0 a v ss 5887.0 ?94.0 a v ss ?687.0 ?94.0 a v ss 5987.0 ?94.0 a v ss ?587.0 ?94.0 a v ss 6087.0 ?94.0 a v ss ?487.0 ?94.0 a v ddh 6187.0 ?94.0 a bs ?161.3 ?06.0 a v ddh 6287.0 ?94.0 a bs ?936.4 ?06.0 a v ddh 6387.0 ?94.0 a r/l ?711.3 ?06.0 a v0 6487.0 ?94.0 a r/l ?486.4 ?06.0 a v0 6587.0 ?94.0 a nc ?261.3 ?06.0 a v0 6687.0 ?94.0 a nc ?036.4 ?06.0 a v2 6787.0 ?94.0 a disp ?811.3 ?06.0 a v2 6887.0 ?94.0 a disp ?586.4 ?06.0 a v2 6987.0 ?94.0 a m ?361.3 ?06.0 a v3 7087.0 ?94.0 a m ?136.4 ?06.0 a v3 7187.0 ?94.0 a load ?911.3 ?06.0 a v3 7287.0 ?94.0 a load ?686.4 ?06.0 a v5 7387.0 ?94.0 a cp ?461.3 ?06.0 a v5 7487.0 ?94.0 a cp ?236.4 ?06.0 a v5 7587.0 ?94.0 a eio1 ?011.3 ?06.0 a nc 7687.0 ?94.0 d eio1 ?86.4 ?06.0 a eio2 ?61.3 ?06.0 a eio2 ?36.4 ?06.0 a continued on next page.
no. 6477- 9 /12 LC4132C continued from preceding page. pin x coordinate y coordinate bump type pin x coordinate y coordinate bump type nc ?676.0 ?66.0 b o36 ?577.0 829.0 c nc ?676.0 ?34.0 b o37 ?511.0 829.0 c nc ?676.0 ?02.0 b o38 ?445.0 829.0 c nc ?676.0 ?70.0 b o39 ?379.0 829.0 c nc ?676.0 ?38.0 b o40 ?313.0 829.0 c nc ?676.0 ?.0 b o41 ?247.0 829.0 c nc ?676.0 126.0 b o42 ?181.0 829.0 c o1 ?676.0 258.0 b o43 ?115.0 829.0 c o2 ?676.0 390.0 b o44 ?049.0 829.0 c o3 ?676.0 522.0 b o45 ?983.0 829.0 c o4 ?676.0 654.0 b o46 ?917.0 829.0 c nc ?689.0 829.0 c o47 ?851.0 829.0 c o5 ?623.0 829.0 c o48 ?785.0 829.0 c o6 ?557.0 829.0 c o49 ?719.0 829.0 c o7 ?491.0 829.0 c o50 ?653.0 829.0 c o8 ?425.0 829.0 c o51 ?587.0 829.0 c o9 ?359.0 829.0 c o52 ?521.0 829.0 c o10 ?293.0 829.0 c o53 ?455.0 829.0 c o11 ?227.0 829.0 c o54 ?389.0 829.0 c o12 ?161.0 829.0 c o55 ?323.0 829.0 c o13 ?095.0 829.0 c o56 ?257.0 829.0 c o14 ?029.0 829.0 c o57 ?191.0 829.0 c o15 ?963.0 829.0 c o58 ?125.0 829.0 c o16 ?897.0 829.0 c o59 ?059.0 829.0 c o17 ?831.0 829.0 c o60 ?993.0 829.0 c o18 ?765.0 829.0 c o61 ?927.0 829.0 c o19 ?699.0 829.0 c o62 ?861.0 829.0 c o20 ?633.0 829.0 c o63 ?795.0 829.0 c o21 ?567.0 829.0 c o64 ?729.0 829.0 c o22 ?501.0 829.0 c o65 ?663.0 829.0 c o23 ?435.0 829.0 c o66 ?597.0 829.0 c o24 ?369.0 829.0 c o67 ?531.0 829.0 c o25 ?303.0 829.0 c o68 ?465.0 829.0 c o26 ?237.0 829.0 c o69 ?399.0 829.0 c o27 ?171.0 829.0 c o70 ?333.0 829.0 c o28 ?105.0 829.0 c o71 ?267.0 829.0 c o29 ?039.0 829.0 c o72 ?201.0 829.0 c o30 ?973.0 829.0 c o73 ?135.0 829.0 c o31 ?907.0 829.0 c o74 ?069.0 829.0 c o32 ?841.0 829.0 c o75 ?003.0 829.0 c o33 ?775.0 829.0 c o76 ?937.0 829.0 c o34 ?709.0 829.0 c o77 ?871.0 829.0 c o35 ?643.0 829.0 c o78 ?805.0 829.0 c continued on next page.
no. 6477- 10 /12 LC4132C continued from preceding page. pin x coordinate y coordinate bump type pin x coordinate y coordinate bump type o79 ?739.0 829.0 c o122 99.0 829.0 c o80 ?673.0 829.0 c o123 165.0 829.0 c o81 ?607.0 829.0 c o124 231.0 829.0 c o82 ?541.0 829.0 c o125 297.0 829.0 c o83 ?475.0 829.0 c o126 363.0 829.0 c o84 ?409.0 829.0 c o127 429.0 829.0 c o85 ?343.0 829.0 c o128 495.0 829.0 c o86 ?277.0 829.0 c o129 561.0 829.0 c o87 ?211.0 829.0 c o130 627.0 829.0 c o88 ?145.0 829.0 c o131 693.0 829.0 c o89 ?079.0 829.0 c o132 759.0 829.0 c o90 ?013.0 829.0 c o133 825.0 829.0 c o91 ?947.0 829.0 c o134 891.0 829.0 c o92 ?881.0 829.0 c o135 957.0 829.0 c o93 ?815.0 829.0 c o136 1023.0 829.0 c o94 ?749.0 829.0 c o137 1089.0 829.0 c o95 ?683.0 829.0 c o138 1155.0 829.0 c o96 ?617.0 829.0 c o139 1221.0 829.0 c o97 ?551.0 829.0 c o140 1287.0 829.0 c o98 ?485.0 829.0 c o141 1353.0 829.0 c o99 ?419.0 829.0 c o142 1419.0 829.0 c o100 ?353.0 829.0 c o143 1485.0 829.0 c o101 ?287.0 829.0 c o144 1551.0 829.0 c o102 ?221.0 829.0 c o145 1617.0 829.0 c o103 ?155.0 829.0 c o146 1683.0 829.0 c o104 ?089.0 829.0 c o147 1749.0 829.0 c o105 ?023.0 829.0 c o148 1815.0 829.0 c o106 ?57.0 829.0 c o149 1881.0 829.0 c o107 ?91.0 829.0 c o150 1947.0 829.0 c o108 ?25.0 829.0 c o151 2013.0 829.0 c o109 ?59.0 829.0 c o152 2079.0 829.0 c o110 ?93.0 829.0 c o153 2145.0 829.0 c o111 ?27.0 829.0 c o154 2211.0 829.0 c o112 ?61.0 829.0 c o155 2277.0 829.0 c o113 ?95.0 829.0 c o156 2343.0 829.0 c o114 ?29.0 829.0 c o157 2409.0 829.0 c o115 ?63.0 829.0 c o158 2475.0 829.0 c o116 ?97.0 829.0 c o159 2541.0 829.0 c o117 ?31.0 829.0 c o160 2607.0 829.0 c o118 ?65.0 829.0 c o161 2673.0 829.0 c o119 ?9.0 829.0 c o162 2739.0 829.0 c o120 ?3.0 829.0 c o163 2805.0 829.0 c o121 33.0 829.0 c o164 2871.0 829.0 c continued on next page.
no. 6477- 11 /12 LC4132C continued from preceding page. pin x coordinate y coordinate bump type pin x coordinate y coordinate bump type o165 2937.0 829.0 c o208 5775.0 829.0 c o166 3003.0 829.0 c o209 5841.0 829.0 c o167 3069.0 829.0 c o210 5907.0 829.0 c o168 3135.0 829.0 c o211 5973.0 829.0 c o169 3201.0 829.0 c o212 6039.0 829.0 c o170 3267.0 829.0 c o213 6105.0 829.0 c o171 3333.0 829.0 c o214 6171.0 829.0 c o172 3399.0 829.0 c o215 6237.0 829.0 c o173 3465.0 829.0 c o216 6303.0 829.0 c o174 3531.0 829.0 c o217 6369.0 829.0 c o175 3597.0 829.0 c o218 6435.0 829.0 c o176 3663.0 829.0 c o219 6501.0 829.0 c o177 3729.0 829.0 c o220 6567.0 829.0 c o178 3795.0 829.0 c o221 6633.0 829.0 c o179 3861.0 829.0 c o222 6699.0 829.0 c o180 3927.0 829.0 c o223 6765.0 829.0 c o181 3993.0 829.0 c o224 6831.0 829.0 c o182 4059.0 829.0 c o225 6897.0 829.0 c o183 4125.0 829.0 c o226 6963.0 829.0 c o184 4191.0 829.0 c o227 7029.0 829.0 c o185 4257.0 829.0 c o228 7095.0 829.0 c o186 4323.0 829.0 c o229 7161.0 829.0 c o187 4389.0 829.0 c o230 7227.0 829.0 c o188 4455.0 829.0 c o231 7293.0 829.0 c o189 4521.0 829.0 c o232 7359.0 829.0 c o190 4587.0 829.0 c o233 7425.0 829.0 c o191 4653.0 829.0 c o234 7491.0 829.0 c o192 4719.0 829.0 c o235 7557.0 829.0 c o193 4785.0 829.0 c o236 7623.0 829.0 c o194 4851.0 829.0 c nc 7689.0 829.0 c o195 4917.0 829.0 c o237 7676.0 654.0 b o196 4983.0 829.0 c o238 7676.0 522.0 b o197 5049.0 829.0 c o239 7676.0 390.0 b o198 5115.0 829.0 c o240 7676.0 258.0 b o199 5181.0 829.0 c nc 7676.0 126.0 b o200 5247.0 829.0 c nc 7676.0 ?.0 b o201 5313.0 829.0 c nc 7676.0 ?38.0 b o202 5379.0 829.0 c nc 7676.0 ?70.0 b o203 5445.0 829.0 c nc 7676.0 ?02.0 b o204 5511.0 829.0 c nc 7676.0 ?34.0 b o205 5577.0 829.0 c nc 7676.0 ?66.0 b o206 5643.0 829.0 c o207 5709.0 829.0 c bump type size (x, y) a 60 m 60 m b 75 m 48 m c 48 m 75 m d 72 m 72 m
ps no. 6477- 12 /12 LC4132C this catalog provides information as of may, 2000. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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